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332equ.arc
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RAM.LST
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1990-03-12
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35KB
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606 lines
Motorola 68000 Family Assembler (1.0 ) Mon Mar 12 15:34:03 1990
abs. rel. LC obj. code source line
---- ---- ---- --------- -----------
1 1 0000 |* $RCSfile: ram.sa $
2 2 0000 |* $Revision: 1.1 $
3 3 0000 |* $Date: 90/03/12 13:47:01 $
4 4 0000 |*
5 5 FFFF F000 |REG$ EQU $FFFFF000
6 6 0000 | INCLUDE "DEF.MAC"
7 1i 0000 |
8 2i 0000 |****************************************************************************
9 3i 0000 |* $RCSfile: def.mac $
10 4i 0000 |* $Revision: 1.1 $
11 5i 0000 |* $Date: 90/03/12 13:46:02 $
12 6i 0000 |*
13 7i 0000 |* -------------------------------------------------------------
14 8i 0000 |* Module Name: DEF - Define Symbols Macro
15 9i 0000 |* -------------------------------------------------------------
16 10i 0000 |*
17 11i 0000 |* Description:
18 12i 0000 |* 1. This file contains EQUates and a DEF macro for use with
19 13i 0000 |* MCU's that have internal registers and the bits in those
20 14i 0000 |* registers. By INCLUDE'ing this file with the specific MCU
21 15i 0000 |* equate file(s), mnemonic symbols are defined for the
22 16i 0000 |* internal registers and bits.
23 17i 0000 |* 2. The DEF macro controls how these mnemonic symbols are
24 18i 0000 |* defined. By channeling all symbol definitions through the
25 19i 0000 |* DEF macro, changes made to the DEF macro will affect ALL
26 20i 0000 |* symbol definitions upon re-assembly! See the DEF macro for
27 21i 0000 |* more details.
28 22i 0000 |*
29 23i 0000 |* Notes:
30 24i 0000 |* 1. Motorola reserves the right to make changes to this file.
31 25i 0000 |* Although this file has been carefully reviewed and is
32 26i 0000 |* believed to be reliable, Motorola does not assume any
33 27i 0000 |* liability arising out of its use. This code may be freely
34 28i 0000 |* used and/or modified at no cost or obligation to the user.
35 29i 0000 |* 2. All descriptions are WORD values unless stated otherwise.
36 30i 0000 |* 3. This file was made for use with the Motorola Development
37 31i 0000 |* Systems M68000 Family Structured Assembler for MS-DOS,
38 32i 0000 |* known as M68MASM.
39 33i 0000 |* 4. To use this file, either use an INCLUDE statement or just
40 34i 0000 |* merge this file and the appropriate MCU register equate
41 35i 0000 |* file(s) into your source code file. Consult your assem-
42 36i 0000 |* bler's user's manual for the details specific to your
43 37i 0000 |* situation.
44 38i 0000 |* 5. The latest version of this file is maintained on the
45 39i 0000 |* Motorola FREEWARE Bulletin Board, 512/891-FREE (512/891-
46 40i 0000 |* 3733). It operates continuously (except for maintenance)
47 41i 0000 |* at 1200-2400 baud, 8-bits, no parity. Download the
48 42i 0000 |* archive file <mcu>EQU.ARC to get all the files, where
49 43i 0000 |* <mcu> represents the processor type desired, i.e.
50 44i 0000 |* 332EQU.ARC for MC68332, etc.
51 45i 0000 |*
52 46i 0000 |****************************************************************************
53 47i 0000 |
54 48i 0000 |
55 49i 0000 |* Defines for Bit Definition Types (see DEF macro):
56 50i 0000 |*
57 51i 0000 0001 |BIT$NUM EQU 1 Bit numbers (0-15)
58 52i 0000 0002 |BIT$VAL EQU 2 Bit position values ($0000-$8000)
59 53i 0000 0003 |BIT$BOTH EQU BIT$NUM+BIT$VAL Both bit numbers and values
60 54i 0000 |*
61 55i 0000 0003 |BIT$CODE EQU BIT$BOTH Bit definitions for this assembly!
62 56i 0000 |* NOTE: Change BIT$CODE above to control bit definition types!
63 57i 0000 |
64 58i 0000 |
65 59i 0000 |* Bit Number Equates
66 60i 0000 |*
67 61i 0000 000F |.B15 EQU 15
68 62i 0000 000E |.B14 EQU 14
69 63i 0000 000D |.B13 EQU 13
70 64i 0000 000C |.B12 EQU 12
71 65i 0000 000B |.B11 EQU 11
72 66i 0000 000A |.B10 EQU 10
73 67i 0000 0009 |.B9 EQU 9
74 68i 0000 0008 |.B8 EQU 8
75 69i 0000 0007 |.B7 EQU 7
76 70i 0000 0006 |.B6 EQU 6
77 71i 0000 0005 |.B5 EQU 5
78 72i 0000 0004 |.B4 EQU 4
79 73i 0000 0003 |.B3 EQU 3
80 74i 0000 0002 |.B2 EQU 2
81 75i 0000 0001 |.B1 EQU 1
82 76i 0000 0000 |.B0 EQU 0
83 77i 0000 |
84 78i 0000 |
85 79i 0000 |* Bit Value Equates
86 80i 0000 |*
87 81i 0000 8000 |_B15 EQU 1<<.B15
88 82i 0000 4000 |_B14 EQU 1<<.B14
89 83i 0000 2000 |_B13 EQU 1<<.B13
90 84i 0000 1000 |_B12 EQU 1<<.B12
91 85i 0000 0800 |_B11 EQU 1<<.B11
92 86i 0000 0400 |_B10 EQU 1<<.B10
93 87i 0000 0200 |_B9 EQU 1<<.B9
94 88i 0000 0100 |_B8 EQU 1<<.B8
95 89i 0000 0080 |_B7 EQU 1<<.B7
96 90i 0000 0040 |_B6 EQU 1<<.B6
97 91i 0000 0020 |_B5 EQU 1<<.B5
98 92i 0000 0010 |_B4 EQU 1<<.B4
99 93i 0000 0008 |_B3 EQU 1<<.B3
100 94i 0000 0004 |_B2 EQU 1<<.B2
101 95i 0000 0002 |_B1 EQU 1<<.B1
102 96i 0000 0001 |_B0 EQU 1<<.B0
103 97i 0000 |
104 98i 0000 |
105 99i 0000 |* Mask Value Equates
106 100i 0000 |*
107 101i 0000 FFFF |MSK16 EQU $FFFF 16-bit mask
108 102i 0000 7FFF |MSK15 EQU $7FFF 15-bit mask
109 103i 0000 3FFF |MSK14 EQU $3FFF 14-bit mask
110 104i 0000 1FFF |MSK13 EQU $1FFF 13-bit mask
111 105i 0000 0FFF |MSK12 EQU $0FFF 12-bit mask
112 106i 0000 07FF |MSK11 EQU $07FF 11-bit mask
113 107i 0000 03FF |MSK10 EQU $03FF 10-bit mask
114 108i 0000 01FF |MSK9 EQU $01FF 9-bit mask
115 109i 0000 00FF |MSK8 EQU $00FF 8-bit mask
116 110i 0000 007F |MSK7 EQU $007F 7-bit mask
117 111i 0000 003F |MSK6 EQU $003F 6-bit mask
118 112i 0000 001F |MSK5 EQU $001F 5-bit mask
119 113i 0000 000F |MSK4 EQU $000F 4-bit mask
120 114i 0000 0007 |MSK3 EQU $0007 3-bit mask
121 115i 0000 0003 |MSK2 EQU $0003 2-bit mask
122 116i 0000 0001 |MSK1 EQU $0001 1-bit mask
123 117i 0000 |
124 118i 0000 |
125 119i 0000 |****************************************************************************
126 120i 0000 |* Define Bit Macro:
127 121i 0000 |* Syntax: DEF <name>,<value>[,<field size>[,<reg size>]]
128 122i 0000 |*
129 123i 0000 |* where: <name> is the bit name to be defined.
130 124i 0000 |* <value> is the bit number associated with <name>;
131 125i 0000 |* must be entered as "Bn", where "n" = 0-15.
132 126i 0000 |* <field size> is the optional bit field size starting with
133 127i 0000 |* <value> which must be the least significant
134 128i 0000 |* bit (LSB) of the field. When this parameter
135 129i 0000 |* is present, only the bit field and bit number
136 130i 0000 |* labels are defined.
137 131i 0000 |* <reg size> is the optional size of the register, entered
138 132i 0000 |* as "MSK8" for BYTE sized operands (8-bit).
139 133i 0000 |* The default value is "MSK16" for WORD sized
140 134i 0000 |* operands.
141 135i 0000 |* Action:
142 136i 0000 |* Defines bit number, bit value, or bit field labels based on the
143 137i 0000 |* <name> label and the value of BIT$CODE (defined above).
144 138i 0000 |* Label Key:
145 139i 0000 |* Period prefix (.) denotes bit number label.
146 140i 0000 |* Underscore prefix (_) denotes bit value label.
147 141i 0000 |* Underscore suffix (_) denotes bit field label.
148 142i 0000 |* Underscore MSK suffix (_MSK) denotes bit field mask label.
149 143i 0000 |* Underscore NMSK suffix (_NMSK) denotes not-bit field mask label.
150 144i 0000 |* Label Examples:
151 145i 0000 |* .NAME = bit number label, i.e. 0-15
152 146i 0000 |* _NAME = bit value label, i.e. $0000-$8000
153 147i 0000 |* NAME_ = bit field value label, i.e. $0100 (LSB of field)
154 148i 0000 |* NAME_MSK = bit field mask label, i.e. $0700 (3-bit field)
155 149i 0000 |* NAME_NMSK = bit field not-mask label, i.e. $F8FF (3-bit field)
156 150i 0000 |*
157 151i 0000 |* Notes:
158 152i 0000 |* 1. The "SET" directive is used here instead of the "EQU" directive
159 153i 0000 |* to allow multiple definitions of the same bit labels that are
160 154i 0000 |* used for multiple registers, each with the same values.
161 155i 0000 |* 2. If the user changes the predefined label rules per the Label Key
162 156i 0000 |* above, it is their responsibility to ensure duplicate labels with
163 157i 0000 |* different bit values do not occur!
164 158i 0000 |*
165 159i 0000 |DEF MACRO
166 160i 0000 | IFC "","\3"
167 161i 0000 | IFNE BIT$CODE&BIT$NUM
168 162i 0000 |.\1 SET .\2
169 163i 0000 | ENDC
170 164i 0000 | IFNE BIT$CODE&BIT$VAL
171 165i 0000 |_\1 SET _\2
172 166i 0000 | ENDC
173 167i 0000 | ENDC
174 168i 0000 | IFNC "","\3"
175 169i 0000 |.\1 SET .\2
176 170i 0000 |\1_ SET _\2
177 171i 0000 |\1_MSK SET (MSK\3)<<.\2
178 172i 0000 | IFC "","\4"
179 173i 0000 |\1_NMSK SET (-\1_MSK-1)&MSK16
180 174i 0000 | ENDC
181 175i 0000 | IFNC "","\4"
182 176i 0000 |\1_NMSK SET (-\1_MSK-1)&\4
183 177i 0000 | ENDC
184 178i 0000 | ENDC
185 179i 0000 | ENDM
186 180i 0000 |
187 181i 0000 0000 | IFNE 0 ------- don't assemble unless needed --------
188 182i 0000 | DEF NBL0,B0,4 . nibble 0
189 183i 0000 | DEF NBL1,B4,4 . nibble 1
190 184i 0000 | DEF NBL2,B8,4 . nibble 2
191 185i 0000 | DEF NBL3,B12,4 . nibble 3
192 186i 0000 |
193 187i 0000 | DEF HNBL0,B0,2 . half nibble 0
194 188i 0000 | DEF HNBL1,B2,2 . half nibble 1
195 189i 0000 | DEF HNBL2,B4,2 . half nibble 2
196 190i 0000 | DEF HNBL3,B6,2 . half nibble 3
197 191i 0000 | DEF HNBL4,B8,2 . half nibble 4
198 192i 0000 | DEF HNBL5,B10,2 . half nibble 5
199 193i 0000 | DEF HNBL6,B12,2 . half nibble 6
200 194i 0000 | DEF HNBL7,B14,2 . half nibble 7
201 195i 0000 | ENDC
202 7 0000 | INCLUDE "332RAM.EQU"
203 1i 0000 |
204 2i 0000 |****************************************************************************
205 3i 0000 |* $RCSfile: 332ram.equ $
206 4i 0000 |* $Revision: 1.1 $
207 5i 0000 |* $Date: 90/03/12 13:45:26 $
208 6i 0000 |*
209 7i 0000 |* -------------------------------------------------------------
210 8i 0000 |* Module Name: 332RAM - MC68332 RAM Registers
211 9i 0000 |* -------------------------------------------------------------
212 10i 0000 |*
213 11i 0000 |* Description:
214 12i 0000 |* 1. This file contains EQUates for all the Standby RAM
215 13i 0000 |* Module (RAM) registers and bits for the MC68332. Consult
216 14i 0000 |* the "MC68332 System Integration Module User's Manual", part
217 15i 0000 |* number SIM32UM/AD, for more details.
218 16i 0000 |* 2. A 64-byte address space is reserved for the RAM, though not
219 17i 0000 |* all are used.
220 18i 0000 |* 3. The ABSOLUTE address area where the register array block
221 19i 0000 |* appears in memory is specified by the value of REG$, which
222 20i 0000 |* should be defined in the user's system definitions. The
223 21i 0000 |* value of REG$ is $YFF000, where Y = M111 and M reflects the
224 22i 0000 |* modmap bit (MM) in the module configuration register (MCR).
225 23i 0000 |*
226 24i 0000 |* REG$ value Comments
227 25i 0000 |* ---------- ---------------------------------
228 26i 0000 |* $007FF000 MCR MM bit = 0
229 27i 0000 |* $00FFF000 MCR MM bit = 1 (reset default)
230 28i 0000 |* $FFFFF000 MCR MM bit = 1 (reset default)
231 29i 0000 |* Forces short addressing (unused
232 30i 0000 |* upper address lines are ignored)
233 31i 0000 |* 4. The following pages summarize these registers and their
234 32i 0000 |* associated addresses.
235 33i 0000 |*
236 34i 0000 |* Notes:
237 35i 0000 |* 1. Motorola reserves the right to make changes to this file.
238 36i 0000 |* Although this file has been carefully reviewed and is
239 37i 0000 |* believed to be reliable, Motorola does not assume any
240 38i 0000 |* liability arising out of its use. This code may be freely
241 39i 0000 |* used and/or modified at no cost or obligation to the user.
242 40i 0000 |* 2. All descriptions are WORD values unless stated otherwise.
243 41i 0000 |* 3. The DEF macro along with the BIT$CODE symbol controls the
244 42i 0000 |* actual bit definitions. See the DEF macro in the DEF.MAC
245 43i 0000 |* file for details.
246 44i 0000 |* 4. This file was made for use with the Motorola Development
247 45i 0000 |* Systems M68000 Family Structured Assembler for MS-DOS,
248 46i 0000 |* known as M68MASM.
249 47i 0000 |* 5. To use this file, either use an INCLUDE statement or just
250 48i 0000 |* merge this file into your source code file. Consult your
251 49i 0000 |* assembler's user's manual for the details specific to your
252 50i 0000 |* situation. Reference the code segment example below for
253 51i 0000 |* usage ideas (shown in M68MASM for MS-DOS syntax).
254 52i 0000 |*
255 53i 0000 |* REG$ EQU $FFFFF000 Register base address
256 54i 0000 |* * NOTE: A31-24 unused in MC68332, so we set them all =1
257 55i 0000 |* * in order to use absolute short addressing mode!
258 56i 0000 |* NOLIST
259 57i 0000 |* INCLUDE "DEF.MAC"
260 58i 0000 |* INCLUDE "332RAM.EQU"
261 59i 0000 |* LIST
262 60i 0000 |* START CLR RAM$+RAMTST Absolute addressing!
263 61i 0000 |* LEA RAM$,A6 . OR
264 62i 0000 |* CLR (RAMTST,A6) Indexed addressing!
265 63i 0000 |* * Bit number usage w/indexing!
266 64i 0000 |* BCLR.B #.RAMDS,(RAMBAR+1,A6)
267 65i 0000 |* OR.W (1<<.STOP)+(1<<.RASP),(RAMMCR,A6)
268 66i 0000 |* * . OR
269 67i 0000 |* * Bit value usage w/indexing!
270 68i 0000 |* AND.W #(-_RAMDS-1)&$FFFF,(RAMBAR,A6)
271 69i 0000 |* OR.W _STOP+_RASP,(RAMMCR,A6)
272 70i 0000 |* * Bit field usage w/indexing!
273 71i 0000 |* MOVE.B #(20*SDTEST_),(RAMTST,A6)
274 72i 0000 |* * Bit field mask usage w/indexing!
275 73i 0000 |* MOVE.W (RAMTST,A6),D0
276 74i 0000 |* MOVE.W D0,D1
277 75i 0000 |* AND.W #SDTEST_MSK,D0 Isolate SDTEST field
278 76i 0000 |* MOVE.L #.SDTEST,D2
279 77i 0000 |* LSR.W D2,d0 and right justify it!
280 78i 0000 |* AND.W #SDTEST_NMSK,D1 Clear SDTEST field.
281 79i 0000 |*
282 80i 0000 |* For bit fields, a value (0-N) will be placed inside. As
283 81i 0000 |* can be seen in the last line above, this is accomplished
284 82i 0000 |* by multiplying the bit field label by the desired value
285 83i 0000 |* for the field. This line initializes the RAMTST register
286 84i 0000 |* which has one bit field, SDTEST. This field is initial-
287 85i 0000 |* ized to 20 by this line (places a value of $2800 into the
288 86i 0000 |* RAMTST register).
289 87i 0000 |* 6. Be careful when using any of the BIT instructions (BCHG,
290 88i 0000 |* BCLR, BSET, BTST), as they will only operate on a BYTE of
291 89i 0000 |* memory, not a WORD. Thus to access a bit in the least
292 90i 0000 |* significant half of a word sized register (B0-B7), "+1"
293 91i 0000 |* must be added to the operand address. See the code
294 92i 0000 |* segment example in item 5 above.
295 93i 0000 |* 7. Because the equate files can generate many listing pages,
296 94i 0000 |* the user may wish to disable the listing via NOLIST and
297 95i 0000 |* LIST directives as seen in the above example code.
298 96i 0000 |* 8. The latest version of this file is maintained on the
299 97i 0000 |* Motorola FREEWARE Bulletin Board, 512/891-FREE (512/891-
300 98i 0000 |* 3733). It operates continuously (except for maintenance)
301 99i 0000 |* at 1200-2400 baud, 8-bits, no parity. Download the
302 100i 0000 |* archive file 332EQU.ARC to get all the files.
303 101i 0000 |*
304 102i 0000 |****************************************************************************
305 103i 0000 |
306 104i 0000 |
307 105i 0000 |*********************************************************************
308 106i 0000 |* Define Module Base Address
309 107i 0000 |*********************************************************************
310 108i FFFF FB00 |RAM$ EQU REG$+$B00 RAM base address
311 109i 0000 |
312 110i 0000 |*********************************************************************
313 111i 0000 |* Define Registers and Bits
314 112i 0000 |*********************************************************************
315 113i 0000 0000 |RAMMCR EQU $000 RAM Module Configuration Register
316 114i 0000 | DEF STOP,B15 . stop control
317 1m 0000 + IFC "",""
318 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
319 3m 0000 000F +.STOP SET .B15
320 4m 0000 + ENDC
321 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
322 6m 0000 8000 +_STOP SET _B15
323 7m 0000 + ENDC
324 8m 0000 + ENDC
325 9m 0000 + IFNC "",""
326 10m 0000 +.STOP SET .B15
327 11m 0000 +STOP_ SET _B15
328 12m 0000 +STOP_MSK SET (MSK)<<.B15
329 13m 0000 + IFC "",""
330 14m 0000 +STOP_NMSK SET (-STOP_MSK-1)&MSK16
331 15m 0000 + ENDC
332 16m 0000 + IFNC "",""
333 17m 0000 +STOP_NMSK SET (-STOP_MSK-1)&
334 18m 0000 + ENDC
335 19m 0000 + ENDC
336 115i 0000 | DEF RASP,B8 . RAM array space
337 1m 0000 + IFC "",""
338 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
339 3m 0000 0008 +.RASP SET .B8
340 4m 0000 + ENDC
341 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
342 6m 0000 0100 +_RASP SET _B8
343 7m 0000 + ENDC
344 8m 0000 + ENDC
345 9m 0000 + IFNC "",""
346 10m 0000 +.RASP SET .B8
347 11m 0000 +RASP_ SET _B8
348 12m 0000 +RASP_MSK SET (MSK)<<.B8
349 13m 0000 + IFC "",""
350 14m 0000 +RASP_NMSK SET (-RASP_MSK-1)&MSK16
351 15m 0000 + ENDC
352 16m 0000 + IFNC "",""
353 17m 0000 +RASP_NMSK SET (-RASP_MSK-1)&
354 18m 0000 + ENDC
355 19m 0000 + ENDC
356 116i 0000 |*-------------------------------------------------------------------*
357 117i 0000 0002 |RAMTST EQU $002 RAM Test Register
358 118i 0000 | DEF SDTEST,B9,7 . soft detect test function (7 bits)
359 1m 0000 + IFC "","7"
360 2m 0000 + IFNE BIT$CODE&BIT$NUM
361 3m 0000 +.SDTEST SET .B9
362 4m 0000 + ENDC
363 5m 0000 + IFNE BIT$CODE&BIT$VAL
364 6m 0000 +_SDTEST SET _B9
365 7m 0000 + ENDC
366 8m 0000 + ENDC
367 9m 0000 + IFNC "","7"
368 10m 0000 0009 +.SDTEST SET .B9
369 11m 0000 0200 +SDTEST_ SET _B9
370 12m 0000 FE00 +SDTEST_MSK SET (MSK7)<<.B9
371 13m 0000 + IFC "",""
372 14m 0000 01FF +SDTEST_NMSK SET (-SDTEST_MSK-1)&MSK16
373 15m 0000 + ENDC
374 16m 0000 + IFNC "",""
375 17m 0000 +SDTEST_NMSK SET (-SDTEST_MSK-1)&
376 18m 0000 + ENDC
377 19m 0000 + ENDC
378 119i 0000 | DEF RTBA,B8 . base address register R/W
379 1m 0000 + IFC "",""
380 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
381 3m 0000 0008 +.RTBA SET .B8
382 4m 0000 + ENDC
383 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
384 6m 0000 0100 +_RTBA SET _B8
385 7m 0000 + ENDC
386 8m 0000 + ENDC
387 9m 0000 + IFNC "",""
388 10m 0000 +.RTBA SET .B8
389 11m 0000 +RTBA_ SET _B8
390 12m 0000 +RTBA_MSK SET (MSK)<<.B8
391 13m 0000 + IFC "",""
392 14m 0000 +RTBA_NMSK SET (-RTBA_MSK-1)&MSK16
393 15m 0000 + ENDC
394 16m 0000 + IFNC "",""
395 17m 0000 +RTBA_NMSK SET (-RTBA_MSK-1)&
396 18m 0000 + ENDC
397 19m 0000 + ENDC
398 120i 0000 |*-------------------------------------------------------------------*
399 121i 0000 0004 |RAMBAR EQU $004 RAM Array Base Address/Status Register
400 122i 0000 |* NOTE: RAMBAR is a WRITE-ONCE register!
401 123i 0000 | DEF RAMBAS,B3,13 . RAM array base addr, A23-A11 (13 bits)
402 1m 0000 + IFC "","13"
403 2m 0000 + IFNE BIT$CODE&BIT$NUM
404 3m 0000 +.RAMBAS SET .B3
405 4m 0000 + ENDC
406 5m 0000 + IFNE BIT$CODE&BIT$VAL
407 6m 0000 +_RAMBAS SET _B3
408 7m 0000 + ENDC
409 8m 0000 + ENDC
410 9m 0000 + IFNC "","13"
411 10m 0000 0003 +.RAMBAS SET .B3
412 11m 0000 0008 +RAMBAS_ SET _B3
413 12m 0000 FFF8 +RAMBAS_MSK SET (MSK13)<<.B3
414 13m 0000 + IFC "",""
415 14m 0000 0007 +RAMBAS_NMSK SET (-RAMBAS_MSK-1)&MSK16
416 15m 0000 + ENDC
417 16m 0000 + IFNC "",""
418 17m 0000 +RAMBAS_NMSK SET (-RAMBAS_MSK-1)&
419 18m 0000 + ENDC
420 19m 0000 + ENDC
421 124i 0000 | DEF RAMDS,B0 . RAM array disable
422 1m 0000 + IFC "",""
423 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
424 3m 0000 0000 +.RAMDS SET .B0
425 4m 0000 + ENDC
426 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
427 6m 0000 0001 +_RAMDS SET _B0
428 7m 0000 + ENDC
429 8m 0000 + ENDC
430 9m 0000 + IFNC "",""
431 10m 0000 +.RAMDS SET .B0
432 11m 0000 +RAMDS_ SET _B0
433 12m 0000 +RAMDS_MSK SET (MSK)<<.B0
434 13m 0000 + IFC "",""
435 14m 0000 +RAMDS_NMSK SET (-RAMDS_MSK-1)&MSK16
436 15m 0000 + ENDC
437 16m 0000 + IFNC "",""
438 17m 0000 +RAMDS_NMSK SET (-RAMDS_MSK-1)&
439 18m 0000 + ENDC
440 19m 0000 + ENDC
441 125i 0000 |*-------------------------------------------------------------------*
442 126i 0000 |*UNUSED EQU $006-$03F Unused positions
443 127i 0000 |*********************************************************************
444 8 0000 |
445 9 0000 | END
445 lines assembled
symbol table:
symbol name attrib. section value
----------- ------- ------- -----
REG$ abs. 0xfffff000
310 @5
BIT$NUM abs. 0x1
423 380 338 318 59 @57
BIT$VAL abs. 0x2
426 383 341 321 59 @58
BIT$BOTH abs. 0x3
61 @59
BIT$CODE abs. 0x3
426 423 383 380 341 338 321 318 @61
.B15 abs. 0xf
319 87 @67
.B14 abs. 0xe
88 @68
.B13 abs. 0xd
89 @69
.B12 abs. 0xc
90 @70
.B11 abs. 0xb
91 @71
.B10 abs. 0xa
92 @72
.B9 abs. 0x9
370 368 93 @73
.B8 abs. 0x8
381 339 94 @74
.B7 abs. 0x7
95 @75
.B6 abs. 0x6
96 @76
.B5 abs. 0x5
97 @77
.B4 abs. 0x4
98 @78
.B3 abs. 0x3
413 411 99 @79
.B2 abs. 0x2
100 @80
.B1 abs. 0x1
101 @81
.B0 abs. 0x0
424 102 @82
_B15 abs. 0x8000
322 @87
_B14 abs. 0x4000
@88
_B13 abs. 0x2000
@89
_B12 abs. 0x1000
@90
_B11 abs. 0x800
@91
_B10 abs. 0x400
@92
_B9 abs. 0x200
369 @93
_B8 abs. 0x100
384 342 @94
_B7 abs. 0x80
@95
_B6 abs. 0x40
@96
_B5 abs. 0x20
@97
_B4 abs. 0x10
@98
_B3 abs. 0x8
412 @99
_B2 abs. 0x4
@100
_B1 abs. 0x2
@101
_B0 abs. 0x1
427 @102
MSK16 abs. 0xffff
415 372 @107
MSK15 abs. 0x7fff
@108
MSK14 abs. 0x3fff
@109
MSK13 abs. 0x1fff
413 @110
MSK12 abs. 0xfff
@111
MSK11 abs. 0x7ff
@112
MSK10 abs. 0x3ff
@113
MSK9 abs. 0x1ff
@114
MSK8 abs. 0xff
@115
MSK7 abs. 0x7f
370 @116
MSK6 abs. 0x3f
@117
MSK5 abs. 0x1f
@118
MSK4 abs. 0xf
@119
MSK3 abs. 0x7
@120
MSK2 abs. 0x3
@121
MSK1 abs. 0x1
@122
DEF macro
421 401 378 358 336 316
RAM$ abs. 0xfffffb00
@310
RAMMCR abs. 0x0
@315
.STOP abs. 0xf
@319
_STOP abs. 0x8000
@322
.RASP abs. 0x8
@339
_RASP abs. 0x100
@342
RAMTST abs. 0x2
@357
.SDTEST abs. 0x9
@368
SDTEST_ abs. 0x200
@369
SDTEST_MSK abs. 0xfe00
372 @370
SDTEST_NMSK abs. 0x1ff
@372
.RTBA abs. 0x8
@381
_RTBA abs. 0x100
@384
RAMBAR abs. 0x4
@399
.RAMBAS abs. 0x3
@411
RAMBAS_ abs. 0x8
@412
RAMBAS_MSK abs. 0xfff8
415 @413
RAMBAS_NMSK abs. 0x7
@415
.RAMDS abs. 0x0
@424
_RAMDS abs. 0x1
@427
74 symbols
